Now I can do the synthesis, correctly assign the I/O ports of the processor and run the implementation. I changed the delay addition mode to "skew adds through MMCM". I suggest you strip out the constraints for now, work on getting everything hooked up correctly. I use xczu2cg-sfvc784, U8 this is RGMII_txc.That's why I used EMIO pins instead of, for example, MIO to have some possibility of changes, without interfering with the hardware. I will provide a table with connections, it will be more convenient. The schematic only shows the pin connection exactly as I threw in the screenshot above and the power supply for the PHY IC. After that go back and start adding the constraints. So if you can get your design to build without constraints here then that's a good start. That should only affect your timing constraints. Since your PHY defaults to adding the delay start in that mode. That said, your timings absolutely do need to change depending on whether the PHY is providing those delays or the MAC is. Presumably that GMII to RGMII block is changing how the create_clock works depending on the mode, and thus the timing constraints no longer match. The initial issue is the clock they are using doesn't exist. It seems to me that the problem is not with the values of the times themselves, written in these time limits. I think the IO pin assignment error is going to be a problem whatever delay mode you use. I don't suppose you can share the schematic? Or a snippet showing the PHY connecting to the FPGA? What do you mean by this? It's a custom board? In which case you probably need to chat to your hardware designer about the pin muxing, if they've hooked this up to something you can't use then that's going to be a problem. It's the original internal hardware design. Where did you get these constraints? You may need to tweak them. If I choose this option, I get a lot of errors after setting the constraints. I can't 100% remember all the details of this, but IIRC it made life a bit simpler to have the PHY add one of those delays but not the other, at least in my case. Writing timing constraints for RGMII buses is pretty complicated, it was my first big timing analysis challenge. You can choose to disable those delays (via MDIO) if you wish. Depending on the delay settings in the MAC, these delays may have to be modified See section 2.4.2 in your PHY's datasheet: īoth Tx and Rx delays are enabled by default. Thank you in advance for your advice and suggestions.Įdit: constraints problem in " skew adds through MMCM ": I can't assign pin U8 as shown in the picture.Ĭan I safely use the "skew added by phy" option? or any other way to run the circuit without changing the hardware? If I choose this option, I get a lot of errors after setting the constraints. However, from what I can see and what I did not know they are not fully interchangeable in my case. Unfortunately, I can't assign all the pins according to the configuration I chose. In the "GMII to RGMII" block, I use the configuration to attach the shared logic in the core. Based on page and PG160, I have prepared a very simple project. I've come to the point where I need to start communication via RGMII with an ETH chip(Marvell 88E1512).
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